The present invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing flash memory devices, wherein it can reduce interference between floating gates.
In a NAND type flash memory device, a plurality of cells for storing data therein are connected in series to form one string. A drain selection transistor and a source selection transistor are formed between the cell string and the drain and between the cell string and the source, respectively. Each cell of the NAND flash memory device constructed above is formed by forming a gate in which a tunnel oxide layer, a floating gate, a dielectric layer and a control gate are laminated on a predetermined region of a semiconductor substrate and forming a junction on both sides of the gate.
In the NAND flash memory device, the status of a cell is influenced by the operations of neighboring cells. It is thus very important to keep constant the status of the cell. A phenomenon in which the status of a cell is changed due to the operations of neighboring cells (more particularly, a program operation) is referred to as an “interference phenomenon”. In other words, the term “interference phenomenon” refers to a phenomenon in which if a first cell to be programmed and a second cell adjacent to the first cell are programmed, a threshold voltage higher than that of the first cell when the first cell is read is read due to a capacitance effect caused by variation in the charge of a floating gate of the second cell. Though the charge of the floating gate of the read cell is not changed, the status of an actual cell looks distorted due to the change in the status of an adjacent cell. The status of the cell is varied because of the interference phenomenon. It results in an increased defective ratio and a decreased yield. Accordingly, to minimize the interference phenomenon is effective in keeping constant the status of the cell.
Meanwhile, in a general manufacture process of a NAND flash memory device, portions of an isolation layer and a floating gate are formed using a Self-Aligned Shallow Trench Isolation (SA-STI) process. The process will be described below in short with reference to FIG. 1.
A tunnel oxide layer 11 and a first polysilicon layer 12 are formed on a semiconductor substrate 10. Predetermined regions of the first polysilicon layer 12 and the tunnel oxide layer 11 are etched. The semiconductor substrate 10 is etched to a depth, forming trenches 13. The trenches are gap-filled with an insulating layer. A polishing process is performed to form isolation layers 14. Thereafter, a first oxide layer 15, a nitride layer 16 and a second oxide layer 17 are sequentially formed, completing a dielectric layer 18.
If the flash memory device is fabricated by the SA-STI process as described above, the isolation layer is formed between the first polysilicon layer serving as the floating gate and an adjacent first polysilicon layer. Accordingly, interference may occur between the first polysilicon layers.
FIG. 2 is a graph showing the relationship between the interference phenomenon depending on a height and distance between the floating gates, and the coupling ratio.
From FIG. 2, it can be seen that the interference between the gates is proportional to the distance between the floating gates and the height of the floating gate. In other words, if the distance between the floating gates is far and the height of the floating gate is decreased, the interference is decreased. However, if the height of the floating gate is reduced, the interfacial area of the floating gate and the control gate is reduced and the coupling ratio is reduced.